Parallel algorithms for detecting hazards in combinational logic circuits

被引：0
|
作者：
Tan, EC [1 ]
机构：
[1] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
来源：
IEEE 2000 TENCON PROCEEDINGS, VOLS I-III: INTELLIGENT SYSTEMS AND TECHNOLOGIES FOR THE NEW MILLENNIUM | 2000年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Data and control parallelism algorithms are described for a matrix method which detects and locates the presence of logic hazards in combinational logic circuits. Examples are given for illustration.
引用
收藏
页码：177 / 181
页数：5
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