WIRELENGTH DRIVEN PLACEMENT FOR FPGA USING SOFT COMPUTING TECHNIQUE

被引：0
|
作者：
Venuopal, Nagalakshmi [1 ]
Manimegalai, R. [2 ]
机构：
[1] Dr NGP Inst Technol, Coimbatore, Tamil Nadu, India
[2] Pk Coll Engn & Technol, Coimbatore, Tamil Nadu, India
来源：
PROCEEDINGS OF THE IEEE INTERNATIONAL CONFERENCE ON SOFT-COMPUTING AND NETWORKS SECURITY (ICSNS 2015) | 2015年
关键词：
FPGA; Placer; Placement; Optimization; Routing;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Placement is the one of the important step in the Field Programmable Gate Array (FPGA) design flow. A successful placement provides complete and optimal routing for the circuit that is to be configured on the FPGA. In this paper an efficient placement algorithm based on Particle Swarm Optimization (PSO), PSO_Placer, is proposed. The proposed PSO based Placement algorithm focuses on minimizing the wirelength and channel width. The results obtained using proposed PSO based placement algorithm is encouraging when compared to existing placement techniques for FPGA.
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页数：5
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