Fully parallel ANN-based arrhythmia classifier on a single-chip FPGA: FPAAC

Recognition of cardiac arrhythmias by electrocardiogram (ECG) is an important issue for diagnosis of cardiac abnormalities. Many studies on recognition of cardiac arrhythmias by ECG, using various techniques, have been performed in the past 20 years. Artificial neural networks (ANNs) are the most widely used tool in medical diagnosis systems (MDS) because of their powerful prediction characteristics. An ANN model is inspired by real biological neural networks, with a parallel structure that is potentially fast for computation. However, the suggested ANN architectures in the literature can only be run sequentially, on powerful processors, due to their complexity. Our approach enables the implementation of a simple ANN architecture with lower requirements for hardware resources. The features of the ECG signal are reduced dramatically using principle component analysis (PCA) while keeping the error rate of the ANN at an acceptable level, near 5%. To enable the implementation of real ANN models on parallel devices, the features of the ECG signal that are applied to the ANN inputs must be reduced. In this study, field programmable gate arrays (FPGA) implementation of a fully parallel, fault-tolerant ANN for ECG arrhythmia classification (FPAAC) is realized. An ANN model, which consists of 8 inputs, a hidden layer with 2 neurons, and I output neuron, is implemented on an FPGA using IEEE-754 32-bit floating-point numerical representation. FPAAC classifies 3 classes of arrhythmia, premature ventricular contraction (PVC), fusion (F), and normal (N) beats, and its accuracy is 97.66%. The ECG records used in this work were taken from the MIT-BIH arrhythmia database.