Implementation of Sigma-Delta Analog to Digital Converter in FPGA

被引：0

作者：

Mihalov, Jozef ^{[1
]}

Stopjakova, Viera ^{[1
]}

机构：

[1] Slovak Univ Technol Bratislava, Dept Microelect, Fac Elect Engn & Informat Technol, Bratislava, Slovakia

来源：

2011 INTERNATIONAL CONFERENCE ON APPLIED ELECTRONICS (AE) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents implementation of a second-order Sigma-Delta Analog to Digital Converter (ADC) for audio band in field-programmable gate array (FPGA) Xilinx Virtex5. This family of FPGA contains a differential input buffers, which are used to create a continuous-time integrators as a loop filter stages. The implementation is done using hardware description language (VHDL).

引用

页数：4

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