Optoelectronic PLL simulation and optimisation with VHDL-AMS

This paper presents a behavioural model for an optoelectronic Phase Locked Loop. This concept is promising in the context of digital optical communications. It leads to very high frequency clock recovery thanks to the use of optical components, for example a semiconductor optical amplifier is used, as a phase comparator. This kind of complex device modelling and simulation takes advantage of the standardised VHDL-AMS language which is particularly suited for multi-technological systems, with both electrical and optical variables in our case. The VHDL-AMS behavioural model of the complete loop is simulated and results are compared to measurements carried out on a prototype in order to validate the model. We also present the top-down design of a complementary circuit, a variable gain amplifier controlled by the power of the input signal, which optimises the PLL's performances. It results that the capture range is increased to its maximum whatever this power is. Once again, this design is made easier by the VHDL-AMS language, which allows multi-level simulation : transistor level (the complementary circuit) and behavioural level (the rest of the PLL) in the same system.