High-performance, cost-effective 2z nm two-deck cross-point memory integrated by self-align scheme for 128 Gb SCM

被引：0

作者：

Kim, Taehoon ^{[1
]}

Choi, Hyejung ^{[1
]}

Kim, Myoungsub ^{[1
]}

Yi, Jaeyun ^{[1
]}

Kim, Donghoon ^{[1
]}

Cho, Sunglae ^{[1
]}

Lee, Hyunmin ^{[1
]}

Hwang, Changyoun ^{[1
]}

Hwang, Eung-Rim ^{[1
]}

Song, Jeongho ^{[1
]}

Chae, Sujin ^{[1
]}

Chun, Yunseok ^{[1
]}

Kim, Jin-Kook ^{[1
]}

机构：

[1] SK Hynix, R&D Div, Icheon, South Korea

来源：

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a high-performance and cost-effective cross-point memory (CPM) technology for two-deck 128 Gb storage class memory (SCM). The unit MAT size is 16 Mb consisting of a 2z nm 1S1M (one selector one memory) structure that is patterned by only two ArF-i steps per deck for a low cost per bit. The formidable task of self-align etch is enabled by the use of state-of-the-art etching and integration technology, which otherwise easily leads to hard fail or poor cell characteristics and reliabilities. New phase change materials (N-PCMs) are developed to have a large V-t window and a uniform V-t distribution for a sufficient read window margin (RWM) and a corresponding low raw bit error rate (RBER). New chalcogenide selectors (NCSs) are also developed to provide low V-t instability and very low leakage current. The new CPM is able to provide a sufficient RWM for 16 Mb MATs with very low latencies of write (set <= 300 ns) and read (<= 100 ns). We also demonstrate its decent write disturbance and high reliabilities such as endurance and thermal retention.

引用

页数：4