BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs

被引：45

作者：

Dasgupta, Avirup ^{[1
]}

Parihar, Shivendra Singh ^{[2
]}

Kushwaha, Pragya ^{[1
]}

Agarwal, Harshit ^{[3
]}

Kao, Ming-Yen ^{[1
]}

Salahuddin, Sayeef ^{[1
]}

Chauhan, Yogesh Singh ^{[2
]}

Hu, Chenming ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

[2] IIT Kanpur, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India

[3] IIT Jodhpur, Dept Elect Engn, Jodhpur 342037, Rajasthan, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2020年 / 67卷 / 02期

关键词：

Bandgap; compact model; dimension; density of states (DOS); effective mass; gate-all-around; nanosheet; nanowire; quantum capacitance; SPICE; subband energy; NANOWIRE; CHARGE;

D O I：

10.1109/TED.2019.2960269

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a compact model for nanosheet FETs that take the effects of quantum confinement into account. The model captures the nanosheet width and thickness dependence of the electrostatic dimension, density of states, effective mass, subband energies, and threshold voltages and includes them in the charge calculation, resulting in an accurate terminal charge and current characteristics. The model has been implemented using Verilog-A in the BSIM-CMG framework for all simulations. It has been validated with band-structure calculation-based TCAD simulations as well as measured data. We have also highlighted the significance of quantum mechanical effects on analog and RF performance of the device.

引用

页码：730 / 737

页数：8

共 22 条

[1]

[Anonymous], FINFET MODELING IC S

[2]

[Anonymous], 2006, YEARB SOUTH ASIAN

[3]

[Anonymous], THE K P METHOD

[4]

Bae G, 2018, INT EL DEVICES MEET

[5]

Barraud S., 2018, P 2018 IEEE INT EL D, P500, DOI [10.1109/IEDM.2018.8614507, DOI 10.1109/IEDM.2018.8614507]

[6] High performance silicon nanowire field effect transistors [J].

Cui, Y ;

Zhong, ZH ;

Wang, DL ;

Wang, WU ;

Lieber, CM .

NANO LETTERS, 2003, 3 (02) :149-152

[7] Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition [J].

Dasgupta, Avirup ;

Rastogi, Priyank ;

Agarwal, Amit ;

Hu, Chenming ;

Chauhan, Yogesh Singh .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) :1094-1100

[8] Unified Compact Model for Nanowire Transistors Including Quantum Effects and Quasi-Ballistic Transport [J].

Dasgupta, Avirup ;

Agarwal, Amit ;

Chauhan, Yogesh Singh .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (04) :1837-1845

[9]

Jiang Y, 2008, S VLSI TECH, P27

[10]

Karner M., Tech Dig-Int Electron Devices Meet IEDM, P762, DOI 10.1109/IEDM.2016.7838516

← 1 2 3 →