A software defined radio architecture for a regenerative On-Board Processor

被引:1
作者
Iacomacci, F. [1 ]
Morlet, C. [2 ]
Autelitano, F. [1 ]
Cardarilli, G. C. [3 ]
Re, M. [3 ]
Petrongari, E. [6 ]
Bogo, G. [4 ]
Franceschelli, M. [5 ]
机构
[1] Thales Alenia Space Italy, Via Saccomuro 24, I-00131 Rome, Italy
[2] ESA ESTEC, Noordwijk, Netherlands
[3] Univ Roma Tor Vergata, Rome, Italy
[4] Space Engn, Bristol, Avon, England
[5] START Consortium, College Pk, MD USA
[6] ULISSE Consortium, Taranto, Italy
来源
PROCEEDINGS OF THE 2008 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS | 2008年
关键词
D O I
10.1109/AHS.2008.37
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The possibility to adapt in-flight the behaviour of a space-based equipment to different operating conditions and/or new functional requirements is of paramount importance in the field of the commercial multimedia communications. Infact, in a satellite lifetime of 15 years, new standards may arise, the existing one may be upgraded, or the opportunity to introduce new added-value services may be considered by a satellite operator. The in-flight adaptability is particularly significant for an On-Board Processor (OBP) based on the signal regeneration: such kind of equipments, though offering excellent performances in terms of BER/PER, require an access protocol to exploit the communication resources and this condition is an heavy limitation to the OBP flexibility, usually perceived as a risk factor by a commercial satellite operator. The present paper describes a Regenerative OBP architecture which makes use of the SRAM-based FPGA technology to obtain a fully reconfigurable platform, where any functional block Of the signal processing chain may be completely modified in-flight. Together with the OBP architecture, a procedure to perform an efficient and reliable payload reconfiguration is described A prototype of the proposed OBP architecture, based on COTS devices, will be realized in the frame of an ESA/ESTEC contract.
引用
收藏
页码:164 / +
页数:2
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