Parallel loopback test of mixed-signal circuits

被引:9
作者
Park, Joonsung [1 ]
Shin, Hongjoong [2 ]
Abraham, Jacob A. [1 ]
机构
[1] Univ Texas Austin, Comp Engn Res Ctr, Austin, TX 78712 USA
[2] Texas Instruments Inc, Austin, TX USA
来源
26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2008年
关键词
D O I
10.1109/VTS.2008.53
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Parallel testing of mixed-signal circuits has been considered a difficult task due to the limited resources in generating and analyzing multiple analog signals. A number of methods have been proposed to perform parallel testing of mixed-signal circuits using built-in test circuitry; however, these techniques are vulnerable to fault masking issues which may degrade the test accuracy. This paper presents an efficient parallel test algorithm for mixed-signal circuits based on a loopback test method. Multiple DUTs (Devices Under Test) are loopbacked externally on a loadboard which is loaded with a simple analog adder and an RMS detector The performance parameters of each DUT are calculated separately from the composite responses, while removing the effect of fault masking. Parallelism is increased by sharing common test equipment and a DUT loadboard among the multiple DUTs. The mathematical theory and simulation results are presented to validate our algorithm.
引用
收藏
页码:309 / +
页数:2
相关论文
共 24 条
[1]  
*ADV, ADV MIX SIGN TEST SY
[2]  
Bogard H, 1995, PROCEEDINGS - INTERNATIONAL TEST CONFERENCE 1995, P370, DOI 10.1109/TEST.1995.529862
[3]  
Burns M., 2001, INTRO MIXED SIGNAL I
[4]   Mixed loopback BiST for RF digital transceivers [J].
Dabrowski, J ;
Bayon, JG .
19TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2004, :220-228
[5]   On-chip analog signal generator for mixed-signal Built-In Self-Test [J].
Dufort, B ;
Roberts, GW .
IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, :549-552
[6]   A stand-alone integrated excitation/extraction system for analog BIST applications [J].
Hafed, MM ;
Roberts, GW .
PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2000, :83-86
[7]   A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs [J].
Kerzerho, Vincent ;
Cauvet, Philippe ;
Bernard, Serge ;
Azais, Florence ;
Comte, Mariane ;
Renovell, Michel .
IEEE DESIGN & TEST OF COMPUTERS, 2006, 23 (03) :234-243
[8]   Transformer-coupled loopback test for differential mixed-signal specifications [J].
Kim, Byoungho ;
Fu, Zhenhai ;
Abraham, Jacob A. .
25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, :291-+
[9]  
KWAN J, 2006, P INT TEST C, P1
[10]  
Le J., 2006, P INT TEST C, P1