共 25 条
[1]
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell
[J].
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST,
2004,
:657-660
[3]
THERMAL STABILIZATION OF DEVICE QUALITY FILMS DEPOSITED AT LOW-TEMPERATURES
[J].
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A-VACUUM SURFACES AND FILMS,
1990, 8 (03)
:1871-1877
[4]
Ghani T., 2003, IEEE International Electron Devices Meeting 2003, p11.6.1, DOI 10.1109/IEDM.2003.1269442
[5]
Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs
[J].
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST,
2004,
:209-212
[7]
HIRAO S, 1993, SOL STAT DEV MAT, P826
[8]
Mobility improvement for 45mn node by combination of optimized stress control and channel orientation design
[J].
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST,
2004,
:217-220