Exploiting Non-Leading Zeroes to Reduce Energy Consumption for Non-Volatile Memories

被引:2
作者
Choi, Juhee [1 ]
Park, Heemin [2 ]
机构
[1] Sangmyung Univ, Dept Smart Informat Commun Engn, 31 Sangmyungdae Gil, Cheonan 31066, South Korea
[2] Sangmyung Univ, Dept Software, 31 Sangmyungdae Gil, Cheonan 31066, South Korea
关键词
non-volatile memory; STT-RAM; low power scheme; cache;
D O I
10.1002/tee.23512
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The penalty of write operations is one of the main hindrances for adopting nonvolatile memory for IoT devices. As a solution for mitigating this problem, the read-before-write scheme is proposed to prevent unnecessary writing by comparing all bits to be written with the existing values. However, this approach also generates additional read accesses for every write access. To reduce these read operations, we design a zero-bit pattern scheme that deactivates bit cells indicated as zero bits during access to the cache. In our experiments, the dynamic energy consumption is decreased by 35.0% with 2.3% additional storage. (c) 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.
引用
收藏
页码:305 / 307
页数:3
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