High-performance three-dimensional on-chip inductors in SOICMOS technology for monolithic RF circuit applications

被引：0

作者：

Kim, J ^{[1
]}

Plouchart, JO ^{[1
]}

Zamdmer, N ^{[1
]}

Fong, N ^{[1
]}

Lu, LH ^{[1
]}

Tan, Y ^{[1
]}

Jenkins, KA ^{[1
]}

Sherony, M ^{[1
]}

Groves, R ^{[1
]}

Kumar, M ^{[1
]}

Ray, A ^{[1
]}

机构：

[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA

来源：

2003 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3 | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 mum SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH/mum(2) is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.

引用

页码：A77 / A80

页数：4

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