Synthesis of a 12-bit complex mixer for FPGA implementation

被引：0

作者：

Liu, Q ^{[1
]}

Langlois, JMP ^{[1
]}

Al-Khalili, D ^{[1
]}

Szwarc, V ^{[1
]}

Inkol, R ^{[1
]}

机构：

[1] Royal Mil Coll Canada, Kingston, ON, Canada

来源：

CCECE 2003: CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3, PROCEEDINGS: TOWARD A CARING AND HUMANE TECHNOLOGY | 2003年

关键词：

complex mixer; complex multiplier; direct digital frequency synthesizer; FPGA implementation;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a FPGA implementation of a multiplier-based complex mixer for communication systems that require high-throughput rates and architecture scalability. The paper focuses on the design of a complex mixer that consists of a Baugh-Wooley-Adder-Tree complex multiplier and a Direct Digital Frequency Synthesizer (DDFS) based on a linear segment interpolation algorithm. The regular structure of this architecture permits deep pipelining and facilitates scaling to meet a given system specification.

引用

页码：81 / 84

页数：4