A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities

被引:25
作者
Jafari, Ali [1 ]
Buswell, Nathanael [1 ]
Ghovanloo, Maysam [2 ]
Mohsenin, Tinoosh [1 ]
机构
[1] Univ Maryland Baltimore Cty, Comp Sci & Elect Engn Dept, Baltimore, MD 21250 USA
[2] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
基金
美国国家科学基金会;
关键词
ASIC; assistive technology; field programmable gate array (FPGA); low-power; machine learning classifiers; paralysis; tongue drive system; HUMAN-COMPUTER INTERFACE; ASSISTIVE TECHNOLOGY; DEVICE; BLIND;
D O I
10.1109/TBCAS.2017.2757031
中图分类号
R318 [生物医学工程];
学科分类号
0831 ;
摘要
This paper presents a low-power stand-alone tongue drive system (sTDS) used for individuals with severe disabilities to potentially control their environment such as computer, smartphone, and wheelchair using their voluntary tongue movements. A low-power local processor is proposed, which can perform signal processing to convert raw magnetic sensor signals to user-defined commands, on the sTDS wearable headset, rather than sending all raw data out to a PC or smartphone. The proposed sTDS significantly reduces the transmitter power consumption and subsequently increases the battery life. Assuming the sTDS user issues one command every 20 ms, the proposed local processor reduces the data volume that needs to be wirelessly transmitted by a factor of 64, from 9.6 to 0.15 kb/s. The proposed processor consists of three main blocks: serial peripheral interface bus for receiving raw data from magnetic sensors, external magnetic interference attenuation to attenuate external magnetic field from the raw magnetic signal, and a machine learning classifier for command detection. A proof-of-concept prototype sTDS has been implemented with a low-power IGLOO-nano field programmable gate array (FPGA), bluetooth low energy, battery and magnetic sensors on a headset, and tested. At clock frequency of 20 MHz, the processor takes 6.6 mu s and consumes 27 nJ for detecting a command with a detection accuracy of 96.9%. To further reduce power consumption, an application-specified integrated circuit processor for the sTDS is implemented at the postlayout level in 65-nm CMOS technology with 1-V power supply, and it consumes 0.43 mW, which is 10x lower than FPGA power consumption and occupies an area of only 0.016 mm(2)
引用
收藏
页码:58 / 67
页数:10
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