A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

被引：0

作者：

Cai, Zhikuang ^{[1
]}

Que, Shixuan ^{[2
]}

Liu, Tingting ^{[2
]}

Xu, Haobo ^{[2
]}

机构：

[1] Nanjing Univ Posts & Telecommun, Coll Elect Sci & Engn, Nanjing 210046, Jiangsu, Peoples R China

[2] Southeast Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing 210096, Jiangsu, Peoples R China

来源：

PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS RESEARCH AND MECHATRONICS ENGINEERING | 2015年 / 121卷

关键词：

PLL; BIST; jitter; fault model; production test; parametric test; PHASE-LOCKED LOOPS; IN SELF-TEST;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a hybrid built-in self-test (BIST) scheme is firstly proposed for phase-locked loop (PLL) production test and performance characterization. The scheme combines the structure test and function test in production test operation. The former is to detect hard faults and the latter is used to improve the soft fault coverage. Jitter measurement is selected as a typical parameter test in performance characterization mode, which includes vernier delay line (VDL) to measure timing jitter and undersampling technology to measure cycle-cycle jitter. The goal of the scheme is to enable complete production quality test and exact performance characterization.

引用

页码：354 / 357

页数：4

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