Thermo-Mechanical Stress Characterization of Tungsten-Fill Through-Silicon-Via

被引:0
|
作者
Thuy Dao [1 ]
Triyoso, Dina H. [1 ]
Mora, Rode [1 ]
Kropewnicki, Tom [1 ]
Griesbach, Brian [1 ]
Booker, Doug [1 ]
Petras, Mike [2 ]
Adams, Vance [2 ]
机构
[1] Freescale Semicond, Austin, TX 78735 USA
[2] Freescale Semicond, Tempe, AZ USA
关键词
3D INTEGRATION;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2 mu m) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30 mu m length the stress is 45% greater compared to the case of 7 mu m length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.
引用
收藏
页码:7 / 10
页数:4
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