Comparative analysis of yield optimized pulsed flip-flops

被引：22

作者：

Lanuzza, Marco ^{[1
]}

De Rose, Raffaele ^{[1
]}

Frustaci, Fabio ^{[1
]}

Perri, Stefania ^{[1
]}

Corsonello, Pasquale ^{[1
]}

机构：

[1] Univ Calabria, Dept Elect Comp Sci & Syst, I-87036 Arcavacata Di Rende, CS, Italy

来源：

MICROELECTRONICS RELIABILITY | 2012年 / 52卷 / 08期

关键词：

DELAY-AREA DOMAIN; NANOMETER CMOS; IMPACT; VARIABILITY;

D O I：

10.1016/j.microrel.2012.03.024

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte Carlo simulation results demonstrate that using transistor reordering and dual threshold voltage transistors timing, energy and energy-delay-product yields of more than 1.98, 1.62 and 1.99 times higher are obtained, without requiring architectural modifications and without increasing silicon area requirement. Several flip-flops optimized as described here are compared taking into account the effects due to random process variations and to environmental variations (caused by power supply voltage and temperature fluctuations). Obtained results show that among the compared circuits the Conditional Precharge Flip-Flop achieves the highest delay, energy and energy-delay-product yields. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：1679 / 1689

页数：11

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