PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub quarter micron CMOS technology

被引：37

作者：

Maiti, B ^{[1
]}

Tobin, PJ ^{[1
]}

Hobbs, C ^{[1
]}

Hegde, RI ^{[1
]}

Huang, F ^{[1
]}

O'Meara, DL ^{[1
]}

Jovanovic, D ^{[1
]}

Mendicino, M ^{[1
]}

Chen, J ^{[1
]}

Connelly, D ^{[1
]}

Adetutu, O ^{[1
]}

Mogab, J ^{[1
]}

Candelaria, J ^{[1
]}

La, LB ^{[1
]}

机构：

[1] Motorola Inc, Adv Prod Res & Dev Lab, Austin, TX 78721 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746472

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with TiN gate. Issues associated with Leff and reliability are also discussed.

引用

页码：781 / 784

页数：4

共 9 条

[1]

[Anonymous], IEDM

[2]

COLINGE JP, 1991, SOI TECHNOLOGY MAT V

[3] Gate oxide scaling limits and projection [J].

Hu, CM .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :319-322

[4] Feasibility of using W/TiN as metal gate for conventional 0.13μm CMOS technology and beyond [J].

Hu, JC ;

Yang, H ;

Kraft, R ;

Rotondaro, ALP ;

Hattangady, S ;

Lee, WW ;

Chapman, RA ;

Chao, CP ;

Chatterjee, A ;

Hanratty, M ;

Rodder, M ;

Chen, IC .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :825-828

[5] Simultaneous auctions with synergies [J].

Krishna, V ;

Rosenthal, RW .

GAMES AND ECONOMIC BEHAVIOR, 1996, 17 (01) :1-31

[6] Protocol specification using parameterized communicating extended finite state machines - A case study of the ATM ABR rate control scheme [J].

Lee, D ;

Ramakrishnan, KK ;

Moh, WM ;

Shankar, AU .

1996 INTERNATIONAL CONFERENCE ON NETWORK PROTOCOLS, PROCEEDINGS, 1996, :208-217

[7]

Luo MSC, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P691, DOI 10.1109/IEDM.1995.499313

[8] Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications [J].

Shimada, H ;

Hirano, Y ;

Ushiki, T ;

Ino, K ;

Ohmi, T .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (11) :1903-1907

[9] A comparison of TIN processes for CVD W/TiN gate electrode on 3nm gate oxide [J].

Yang, H ;

Brown, GA ;

Hu, JC ;

Lu, JP ;

Kraft, R ;

Rotondaro, ALP ;

Hattangady, SV ;

Chen, IC ;

Luttmer, JD ;

Chapman, RA ;

Chen, PJ ;

Tsai, HL ;

Amirhekmat, B ;

Magel, LK .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :459-462

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