A simulation study of IC layout effects on thermal management of die attached GaAsICs

Power management and thermal characterization of integrated power amplifiers is crucial to the development of a number of advanced technologies including portable wireless applications. Reduction and or optimization of device operating temperatures and thermal characteristics is needed to control temperature activated failure phenomena. This paper presents the use of PATRAN a three-dimensional (3-D) model builder and finite element method (FEM) solver as means of understanding the heat flow in integrated devices and optimizing the layout for thermal operation. The approach taken is to assume a priori knowledge of the heat generation region and decouple the semiconductor transport equations. This allows for solution of the heat equation over a sufficiently large region to be correct. After verifying the correctness of the assumption of the device temperature being relatively insensitive to the depth, thickness and shape of the heat generation region, the optimization of heat spreaders in a GaAs HBT process is presented. This optimization is performed as an example of how both the maximum temperature and temperature variation across the emitter can reduced by careful design of the emitter metallization, Finally, the use of PATRAN is presented for extracting a three resistor thermal model for two devices in close proximity.