Micron and submicron patterning of polydimethylsiloxane resists on electronic materials by decal transfer lithography and reactive ion-beam etching: Application to the fabrication of high-mobility, thin-film transistors

被引:113
作者
Ahn, Heejoon
Lee, Keon Jae
Childs, William R.
Rogers, John A.
Nuzzo, Ralph G. [1 ]
Shim, Anne
机构
[1] Univ Illinois, Dept Chem, Urbana, IL 61801 USA
[2] Univ Illinois, Dept Mat Sci & Engn, Urbana, IL 61801 USA
[3] Univ Illinois, Beckman Inst, Urbana, IL 61801 USA
[4] Univ Illinois, Frederick Seitz Mat Res Lab, Urbana, IL 61801 USA
[5] Hanyang Univ, Dept Mol Syst Engn, Seoul 133791, South Korea
[6] Hanyang Univ, Grad Sch Fiber & Polymer Engn, Seoul 133791, South Korea
[7] Dow Corning Corp, Auburn, MI 48611 USA
关键词
SOFT LITHOGRAPHY; MICROSTRUCTURES; SURFACES; IMPRINT; SCALE; FEATURES; STAMP; STEP; GOLD;
D O I
10.1063/1.2356784
中图分类号
O59 [应用物理学];
学科分类号
摘要
We describe a technique for fabricating micron and submicron-sized polydimethylsiloxane (PDMS) patterns on electronic material substrates using decal transfer lithography (DTL) in conjunction with reactive ion-beam etching (RIE). We validate the use of this unconventional polymeric system as a suitable resist material for fabricating Si-based microelectronic devices. In this process, an O-2/CF4 gas mixture was used to etch a supporting PDMS thin film that resides atop a closed-form decal polymer to reveal conventional resist structures. These structures provide an effective latent image that, in turn, provides for an extension of soft lithography as a form of multilayer lithography-one yielding submicron structures similar to those obtained from the conventional photochemical methods used to prepare such resists. This combined DTL/RIE patterning procedure was found to be compatible with commercially available planarization layers and provides a direct means for preparing high aspect ratio resist features. We illustrate the applicability of soft lithography as a means for fabricating electronic devices by using it to prepare model silicon-based thin-film transistors exploiting silicon-on-insulator wafer technology. (c) 2006 American Institute of Physics.
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页数:7
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