Ultralow-Power TFT With Gate Oxide Fabricated by Nitric Acid Oxidation Method

被引:9
作者
Matsumoto, Taketoshi [1 ,2 ]
Kubota, Yasushi [3 ,4 ]
Yamada, Mikihiro [1 ,2 ]
Tsuji, Hiroshi [5 ,6 ]
Shimatani, Takafumi [7 ,8 ]
Hirayama, Yasuhiro [7 ,8 ]
Terakawa, Sumio [1 ,2 ]
Imai, Shigeki [7 ,8 ]
Kobayashi, Hikaru [1 ,2 ]
机构
[1] Osaka Univ, Inst Sci & Ind Res, Ibaraki 5670047, Japan
[2] Japan Sci & Technol Agcy, CREST, Ibaraki 5670047, Japan
[3] Sharp Co Ltd, Liquid Crystal Display Grp, Taki 5192192, Japan
[4] Japan Sci & Technol Agcy, CREST, Taki 5192192, Japan
[5] Osaka Univ, Div Elect Elect & Informat Engn, Suita, Osaka 5650871, Japan
[6] Japan Sci & Technol Agcy, CREST, Suita, Osaka 5650871, Japan
[7] Sharp Co Ltd, Display Technol Dev Grp, Nara 6328567, Japan
[8] Japan Sci & Technol Agcy, CREST, Nara 6328567, Japan
关键词
Dielectric films; leakage currents; oxidation; thin-film transistor (TFT); CHEMICAL-VAPOR-DEPOSITION; SILICON DIOXIDE LAYERS; ELECTRICAL CHARACTERISTICS; POLYSILICON TFT; TECHNOLOGY; PECVD;
D O I
10.1109/LED.2010.2050856
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain current-voltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 12-15 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.
引用
收藏
页码:821 / 823
页数:3
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