An x86-64 Core in 32 nm SOI CMOS

被引:18
|
作者
Jotwani, Ravi [1 ]
Sundaram, Sriram [1 ]
Kosonocky, Stephen [2 ]
Schaefer, Alex [1 ]
Andrade, Victor F. [1 ]
Novak, Amy [1 ]
Naffziger, Samuel [2 ]
机构
[1] AMD, Austin, TX 78735 USA
[2] AMD, Ft Collins, CO 80528 USA
关键词
Array design techniques; clock power reduction; electromigration; low power; power gating; power monitor; 64-bit architecture; 8T RAMcell;
D O I
10.1109/JSSC.2010.2080530
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the 32 nm implementation of an AMD x86-64 core [1], [2], [6]. It occupies 9.69 mm(2), contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3 GHz. This AMD chip is fabricated in Global Foundries' 32 nm SOI and uses high-K metal gate technology. The process uses dual strain liners and eSiGe (embedded Silicon Germanium) to improve performance. Transistors are fabricated in various threshold voltages and lengths to facilitate performance/leakage tradeoffs. The core incorporates numerous design and power improvements to enable an operating range of 2.5 W to 25 W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products including multicore SOC designs.
引用
收藏
页码:162 / 172
页数:11
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