A three-stage class AB operational amplifier with enhanced slew rate for switched-capacitor circuits

被引:8
作者
Golabi, Sajad [1 ]
Yavari, Mohammad [1 ]
机构
[1] Amirkabir Univ Technol, Integrated Circuits Design Lab, Dept Elect Engn, Tehran, Iran
关键词
Class AB operation; Three-stage OTAs; Nested Miller compensation; Slew rate; Fast settling; Switched-capacitor circuits; FREQUENCY COMPENSATION; DESIGN PROCEDURE; SETTLING TIME; TRANSCONDUCTANCE;
D O I
10.1007/s10470-015-0513-3
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.
引用
收藏
页码:111 / 118
页数:8
相关论文
共 20 条
[1]   Design procedures for three-stage CMOS OTAs with nested-Miller compensation [J].
Cannizzaro, Salvatore Omar ;
Grasso, Alfio Dario ;
Mita, Rosario ;
Palumbo, Gaetano ;
Pennisi, Salvatore .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (05) :933-940
[2]  
Carusone TC, 2012, ANALOG INTEGR CIRC S, P307
[3]  
Carvajal R. G., 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), P13, DOI 10.1109/ISCAS.2001.921776
[4]   The flipped voltage follower:: A useful cell for low-voltage low-power circuit design [J].
Carvajal, RG ;
Ramírez-Angulo, J ;
López-Martín, A ;
Torralba, A ;
Galán, JAG ;
Carlosena, A ;
Chavero, FM .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (07) :1276-1291
[5]   Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load [J].
Chong, Sau Siong ;
Chan, Pak Kwong .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (09) :2227-2234
[6]   A dynamic zero frequency compensation for 3 A NMOS ultra-low dropout regulator [J].
Dai, Guoding ;
Huang, Chong ;
Yang, Ling .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013, 75 (02) :329-333
[7]  
Eschauzier R.G. H., 1995, Frequency Compensation Techniques for Low-Power Operational Amplifiers
[8]   Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits [J].
Golabi, Sajad ;
Yavari, Mohammad .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2014, 80 (02) :195-208
[9]   A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier [J].
Kim, Young-Ju ;
Lee, Seung-Hoon .
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2012, 72 (01) :75-87
[10]   The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter [J].
Nguyen, Ray ;
Murmann, Boris .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (06) :1244-1254