A 5V Charge Pump in a standard 1.8-V 0.18-μm CMOS process

被引：6

作者：

Hasan, T ^{[1
]}

Lehmann, T ^{[1
]}

Kwok, CY ^{[1
]}

机构：

[1] Univ New S Wales, Sch Elect Engn & Telecommun, Sydney, NSW 2052, Australia

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1464983

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new high voltage tolerant charge pump structure designed with standard low voltage CMOS process is presented in this paper. This fully integrated charge pump design uses a symmetrical structure and can be scaled to achieve higher voltages up to certain limit. The design is based on the standard 1.8-V 0.18-mu m CMOS process without high voltage option. Simulation result shows an output voltage of 5.12 V with a 250 k Omega load and an operating frequency of 2.5 MHz. The efficiency of the circuit is 77% and satisfies typical voltage stress related reliability requirements for low voltage CMOS devices.

引用

页码：1899 / 1902

页数：4

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