A low voltage SRAM for embedded applications

被引：11
|
作者：
Caravella, JS
机构：
[1] Semiconductor Products Sector, Motorola, Tempe
[2] Georgia Institute of Technology, Atlanta, GA
[3] Motorola, Inc., Semiconductor Products Sector, Tempe, AZ
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 03期
关键词：
FET memory integrated circuits; memories; MOS integrated circuits; random access memories;
D O I：
10.1109/4.557643
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an rms run power (1 MHz) of 18 mu W. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 mu W. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.
引用
收藏
页码：428 / 432
页数：5
相关论文
共 50 条
  • [41] Cross-Coupled nFET Preamplifier for Low Voltage SRAM
    Lee, Sangheon
    Park, Jaehyun
    Jeong, Hanwool
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (09) : 3604 - 3608
  • [42] 65NM SUB-THRESHOLD 11T-SRAM FOR ULTRA LOW VOLTAGE APPLICATIONS
    Moradi, Farshad
    Wisland, Dag T.
    Aunet, Snorre
    Mahmoodi, Hamid
    Cao, Tuan Vu
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2008, : 113 - +
  • [43] Low Voltage SRAM Design using Tunneling Regime of CNTFET
    Ahmed, Zubair
    Sarfraz, Khawar
    Zhang, Lining
    Chan, Mansun
    2014 IEEE 14TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2014, : 869 - 872
  • [44] Efficient Voltage Conversion for SRAM Low Standby Power Modes
    Clark, Lawrence T.
    Chen, Tai-Hua
    Chaudhary, Vikas
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 73 - 76
  • [45] Low Power Neural Network by Reducing SRAM Operating Voltage
    Kozu, Keisuke
    Tanabe, Yuya
    Kitakami, Masato
    Namba, Kazuteru
    IEEE ACCESS, 2022, 10 : 116982 - 116986
  • [46] Low Power and Robust Binary Tree SRAM Design for Embedded Systems
    Sun, Luo
    Mathew, Jimson
    Shafik, Rishad A.
    Pradhan, Dhiraj K.
    2013 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED), 2013, : 87 - 92
  • [47] Design of 256-kb low-power embedded SRAM
    Song, Seung-Ho
    Kim, Jung-Hyun
    Lee, Jung-Chan
    Chung, Yeonbae
    EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 313 - 316
  • [48] A 90-nm CMOS Embedded Low Power SRAM Compiler
    Zhang, Zhao-Yong
    Chen, Chia-Cheng
    Zheng, Jian-Bin
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 625 - +
  • [49] Analysis of SRAM Cell Designs for Low Power Applications
    Sharma, Chandresh Kumar
    Chandel, Rajeevan
    2014 INTERNATIONAL CONFERENCE FOR CONVERGENCE OF TECHNOLOGY (I2CT), 2014,
  • [50] Segmented virtual ground architecture for low-power embedded SRAM
    Sharifkhani, Mohammad
    Sachdev, Manoj
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (02) : 196 - 205
12345