A low voltage SRAM for embedded applications

被引：11
|
作者：
Caravella, JS
机构：
[1] Semiconductor Products Sector, Motorola, Tempe
[2] Georgia Institute of Technology, Atlanta, GA
[3] Motorola, Inc., Semiconductor Products Sector, Tempe, AZ
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 03期
关键词：
FET memory integrated circuits; memories; MOS integrated circuits; random access memories;
D O I：
10.1109/4.557643
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an rms run power (1 MHz) of 18 mu W. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 mu W. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.
引用
收藏
页码：428 / 432
页数：5
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