Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies

A low spur frequency synthesiser is proposed based on the frequency-hopping spread spectrum which is employed on the control voltage of the voltage-controlled oscillator. A spur reduction circuit is inserted between the phase-frequency detector and charge pump to randomly shift the spur to higher frequencies to suppress the reference spur. In order to achieve this, the proposed technique uses the time to voltage converter and the voltage to time converter and a linear feedback shift register. Through shifting and randomising the periodic ripples on the control voltage to high frequencies, the amplitude of the reference spur is attenuated. The proposed structure eliminates the need for decreasing bandwidth and reducing the VCO gain to suppress the reference spur. A 2.08-2.22 GHz frequency synthesiser is designed and a post-layout simulation is performed using the 180 nm CMOS technology. The reference spur level of -91.25 dBc is achieved. The presented structure provides an additional spur reduction of 32.88 dB compared to a conventional frequency synthesiser and also provides the best-normalised reference spur rejection in the literature. Settling time is obtainedwhen the output frequency is switched from 2.1 to 2.08 GHz.