Path Based Timing Validation for Timed Asynchronous Design

被引：10

作者：

Lee, William ^{[1
]}

Sharma, Tannu ^{[1
]}

Stevens, Kenneth S. ^{[1
]}

机构：

[1] Univ Utah, Elect & Comp Engn, Salt Lake City, UT 84112 USA

来源：

2016 29TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2016 15TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID) | 2016年

关键词：

D O I：

10.1109/VLSID.2016.111

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Timing is an important parameter necessary to ensure the correctness of a design. Timed asynchronous designs can have complex timing paths that include combinational cycles. Commercial electronic design automation ( EDA) tools do not support asynchronous designs because timing graphs are required to be acyclic. This paper reports on a methodology that enables commercial tools to support full cyclic path timing validation of timed asynchronous designs.

引用

页码：511 / 516

页数：6

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