Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

被引:31
|
作者
Yoon, Jun-Sik [1 ,2 ]
Rim, Taiuk [1 ,2 ]
Kim, Jungsik [3 ]
Kim, Kihyun [1 ,2 ]
Baek, Chang-Ki [1 ,2 ,4 ]
Jeong, Yoon-Ha [4 ]
机构
[1] Pohang Univ Sci & Technol, Dept Creat IT Engn, Pohang 790784, South Korea
[2] Pohang Univ Sci & Technol, Future IT Innovat Lab, Pohang 790784, South Korea
[3] Pohang Univ Sci & Technol, Div IT Convergence Engn, Pohang 790784, South Korea
[4] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 790784, South Korea
关键词
MOBILITY MODEL; SIMULATION; ELECTRON; LEAKAGE; IMPACT;
D O I
10.1063/1.4914976
中图分类号
O59 [应用物理学];
学科分类号
摘要
Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents. (C) 2015 AIP Publishing LLC.
引用
收藏
页数:5
相关论文
共 43 条
  • [1] Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge
    Hong, B. H.
    Cho, N.
    Lee, S. J.
    Yu, Y. S.
    Choi, L.
    Jung, Y. C.
    Cho, K. H.
    Yeo, K. H.
    Kim, D. -W.
    Jin, G. Y.
    Oh, K. S.
    Park, D.
    Song, S. -H.
    Rieh, J. -S.
    Hwang, S. W.
    IEEE ELECTRON DEVICE LETTERS, 2011, 32 (09) : 1179 - 1181
  • [2] Junctionless Versus Inversion-Mode Gate-All-Around Nanowire Transistors From a Low-Frequency Noise Perspective
    Simoen, Eddy
    Veloso, Anabela
    Matagne, Philippe
    Collaert, Nadine
    Claeys, Cor
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (04) : 1487 - 1492
  • [3] Performance Evaluation of Silicon Nanowire Gate-All-Around Field-Effect Transistors and Their Dependence of Channel Length and Diameter
    Bahador, Siti Norazlin
    Tan, Michael Loong Peng
    Ismail, Razali
    SCIENCE OF ADVANCED MATERIALS, 2015, 7 (01) : 190 - 198
  • [4] Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model
    Najam, Faraz
    Yu, Yun Seop
    Cho, Keun Hwi
    Yeo, Kyoung Hwan
    Kim, Dong-Won
    Hwang, Jong Seung
    Kim, Sansig
    Hwang, Sung Woo
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (08) : 2457 - 2463
  • [5] Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors
    Lee, Jae Sung
    Choi, Woo Young
    Kang, In Man
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2012, 51 (06)
  • [6] Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type metal-oxide-semiconductor field-effect transistors
    Kola, Sekhar Reddy
    Li, Yiming
    Thoti, Narasimhulu
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2020, 59 (SG)
  • [7] Random telegraph signal noise in gate-all-around silicon nanowire transistors featuring Coulomb-blockade characteristics
    Zhuge, Jing
    Zhang, Liangliang
    Wang, Runsheng
    Huang, Ru
    Kim, Dong-Won
    Park, Donggun
    Wang, Yangyuan
    APPLIED PHYSICS LETTERS, 2009, 94 (08)
  • [8] Statistical Device Simulation of Characteristic Fluctuation of 10-nm Gate-All-Around Silicon Nanowire MOSFETs Induced by Various Discrete Random Dopants
    Sung, Wen-Li
    Chang, Han-Tung
    Chen, Chieh-Yang
    Chao, Pei-Jung
    Li, Yiming
    2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2016, : 951 - 954
  • [9] Deep Learning Algorithms for the Work Function Fluctuation of Random Nanosized Metal Grains on Gate-All-Around Silicon Nanowire MOSFETs
    Akbar, Chandni
    Li, Yiming
    Sung, Wen-Li
    IEEE ACCESS, 2021, 9 : 73467 - 73481
  • [10] Self-Heating Effect and Characteristic Variability of Gate-All-Around Silicon Nanowire Transistors for Highly-Scaled CMOS Technology (invited)
    Huang, R.
    Wang, R. S.
    Zhuge, J.
    Yu, T.
    Ai, Y. J.
    Fan, C.
    Pu, S. S.
    Zou, J. B.
    Wang, Y. Y.
    2010 IEEE INTERNATIONAL SOI CONFERENCE, 2010,