A fast-settling charge-pump PLL with constant loop bandwidth

被引：7

作者：

Cai, Qingsong ^{[1
,2
]}

Yang, Zhong ^{[1
,2
]}

Zhang, Minglei ^{[1
,2
]}

Jia, Xiaoyun ^{[1
,2
]}

Fan, Xiaohua ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, 3 Beitucheng West Rd, Beijing 100029, Peoples R China

[2] Univ Chinese Acad Sci, 19A Yuquan Rd, Beijing 100049, Peoples R China

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2018年 / 94卷 / 01期

关键词：

Constant loop bandwidth; Synthesizer PLL; VCO gain Kvco; Automatic frequency calibration; LC-VCO; FREQUENCY-SYNTHESIZERS; CALIBRATION;

D O I：

10.1007/s10470-017-1083-3

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump is programmed not only to compensate the variation of voltage-controlled oscillator gain , but also for adapting to the change of divider ratio . This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 A mu m CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is - 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized which is equivalent to the variation of PLL loop bandwidth ranges from - 6 to 6%.

引用

页码：19 / 26

页数：8

共 16 条

[1] ΔΣ PLL transmitter with a loop-bandwidth calibration system [J].