Bridging the HPC Processor-Memory Gap with Quilt Packaging

被引：0
|
作者：
Buckhanan, Wayne L. [1 ]
Niemier, Michael [1 ]
Bernstein, Gary H. [1 ]
机构：
[1] Univ Notre Dame, Ctr Nano Sci & Technol, Notre Dame, IN 46556 USA
来源：
2010 18TH BIENNIAL UNIVERSITY/GOVERNMENT/INDUSTRY MICRO-NANO SYMPOSIUM | 2010年
关键词：
Quilt Packaging; high performance computing; advanced packaging; processor-memory gap;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
High performance computing (HPC) systems are constrained in the areas of performance and power. A new 2D technology, called "Quilt Packaging," is presented as a possible solution to positively impact the processor-memory connection in these areas. A straw man architecture based on a compute node in the Red Storm system at Sandia National Laboratories is used to explore the effects of Quilt Packaging on the connection between processor and memory.
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页数：3
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