Sub-100 nm CMOS circuit performance with high-K gate dielectrics

被引：2

作者：

Mohapatra, NR ^{[1
]}

Dutta, A ^{[1
]}

Sridhar, G ^{[1
]}

Desai, MP ^{[1
]}

Rao, VR ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India

来源：

MICROELECTRONICS RELIABILITY | 2001年 / 41卷 / 07期

关键词：

Capacitance - Computer simulation - Dielectric materials - Gates (transistor) - Integrated circuit testing - Monte Carlo methods - Silica;

D O I：

10.1016/S0026-2714(01)00068-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO2 is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance. (C) 2001 Elsevier Science Ltd. All rights reserved.

引用

页码：1045 / 1048

页数：4

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