Design of Soft Error Tolerance Technique for FPGA Based Soft core Processors

SRAM-based FPGAs are susceptible to radiation induced temporary faults called as single-event upsets (SEUs) or Soft errors. Soft errors affects or changes only some logic states of memory elements, but the device itself is not permanently damaged. SEUs may directly alter the logic states of any static memory element or induce changes to configuration memory. A new fault detection system architecture can be incorporated on any SRAM based FPGA with integrated soft core processors. It allows for detection of error in the system and also detects the processor with the error, so that the system can continue execution with the fault free processor. The fault detection system consists of a Lockstep scheme which is based on DWC technique. Lockstep Scheme detects the presence of error in the system but fails to point in which core, error is present. The Faulty core is detected using RESO Method which is based on DWC-CED technique. Once the faulty core is detected, fault tolerance is achieved using Fault tolerant Configuration Engine and by Hamming method. Fault Tolerant Configuration engine built on the basis of the PicoBlaze core, detects the fault location using CRC method and eliminates the error by frame based reconfiguration and is made fault-tolerant using triple modular redundancy (TMR). SEC using hamming method detects and corrects single bit error. Both the cores are synchronized back after fault recovery using CRB. The coding is done in VHDL language, synthesized using Xilinx ISE 13.2 and simulated using ISim.