Gateway to chips: High speed I/O signalling and interface

The design of inputs and outputs to integrated circuits has traditionally been a straightforward task involving procurement of a specification and its implementation. In the past few technology generations design and implementation of integrated circuit I/O's have become much more complex. Just as Moore's Law predicts that functions per chip will double every 1.5 - 2 years to keep up with consumer demand, there is a corresponding demand for processing electrical signals at progressively higher rates. The International Technology Roadmap for Semiconductors (ITRS) predicts the I/O bandwidth (Gb/s) for high performance ASICs to be 30 Gb/s by the year 2015. Adding to the complexity is the need to conform to a plethora of emerging I/O specifications and continued focus on reliability regarding Electro Static Discharge (ESD) and Simultaneous Switching Noise (SSN), and the circuit designer has about as much challenges as one can stand. This tutorial presents the techniques and methods employed to build a low power, high bandwidth, highly reliable I/O. It covers the popular signaling standards like LVDS, DDR, XAUI and PCI-Express. Also to be covered are concepts of ESD and Signal Integrity. This section of the tutorial will cover the origins of ESD failures in chips, circuit and layout guidelines to avoid ESD failures and ESD testing procedures. Finally, the tutorial will give a detailed architectural overview of various emerging I/O's such as the DDR, LVDS, and the USB-PHY.