Garp: A MIPS processor with a reconfigurable coprocessor

被引：206

作者：

Hauser, JR

Wawrzynek, J

机构：

来源：

5TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES | 1997年

关键词：

D O I：

10.1109/FPGA.1997.624600

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

引用

页码：12 / 21

页数：10