A low-power, high-performance, 1024-point FFT processor

被引：206

作者：

Baas, BM ^{[1
]}

机构：

[1] Stanford Univ, Dept Elect Engn, Star Lab, Stanford, CA 94305 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 03期

基金：

美国国家航空航天局; 美国国家科学基金会;

关键词：

Cache memories; chip; CMOS digital integrated circuits; CMOS integrated circuits; digital signal processors (DSP's); discrete Fourier transforms (DFT's); energy efficient; FFT; Fourier transforms; low power; memory architecture;

D O I：

10.1109/4.748190

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an energy-efficient, single-chip, 1024-point fast Fourier transform (FFT) professor. The 460 000-transistor design has been fabricated in a standard 0.7 mu m (L-poly = 0.6 mu m) CMOS process and is fully functional on first-pass silicon. At a supply voltage of 1.1 V, it calculates a 1024-point complex FFT in 330 mu s while consuming 9.5 mW, resulting in an adjusted energy efficient more than 16 times greater than the previously most efficient known FFT processor. At 3.3 V, it operates at 173 MHz-which is a clock rate 2.6 times greater than the previously fastest rate.

引用

页码：380 / 387

页数：8

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