An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base plus RF)-Band Signaling

被引：37

作者：

Byun, Gyung-Su ^{[1
]}

Kim, Yanghyo ^{[2
]}

Kim, Jongsun ^{[3
]}

Tam, Sai-Wang ^{[4
]}

Chang, Mau-Chung Frank ^{[2
]}

机构：

[1] W Virginia Univ, Lane Dept Comp Sci & Elect Engn, Morgantown, WV 26506 USA

[2] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

[3] Hongik Univ, Sch Elect & Elect Engn, Seoul 121791, South Korea

[4] Marvell Semicond, Santa Clara, CA 95054 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2012年 / 47卷 / 01期

关键词：

Amplitude-shift-keying (ASK); dual-band signaling; impedance transformation; mobile memory interface; multi-band RF-Interconnect (RF-I); simultaneous bidirectional; TRANSCEIVER; CHIP;

D O I：

10.1109/JSSC.2011.2164709

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface. The proposed amplitude shift keying (ASK) modulator/demodulator with on-chip band-selective transformer obviates a power hungry pre-emphasis and equalization circuitry, revealing a low-power, compact and standard mobile memory-compatible solution. Designed and fabricated in 65-nm CMOS technology, each RF-band and baseband transceiver consumes 10.5 mW and 11 mW and occupies 0.08 mm(2) and 0.06 mm(2) die area, respectively. The dual-band transceiver achieves error-free operation (BER <10(-15)) with 2(23) - 1 PRBS at 8.4 Gb/s over a distance of 10 cm.

引用

页码：117 / 130

页数：14

共 17 条

[11] A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme [J].

Oh, Kwang-Il ;

Kim, Lee-Sup ;

Park, Kwang-Il ;

Jun, Young-Hyun ;

Choi, Joo Sun ;

Kim, Kinam .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (08) :2222-2232

[12] A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS [J].

Poulton, John ;

Palmer, Robert ;

Fuller, Andrew M. ;

Greer, Trey ;

Eyles, John ;

Dally, William J. ;

Horowitz, Mark .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (12) :2745-2757

[13]

Tae-Young Oh, 2010, 2010 IEEE International Solid-State Circuits Conference (ISSCC), P434, DOI 10.1109/ISSCC.2010.5433889

[14] A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnects [J].

Wilson, H ;

Haycock, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (12) :1954-1963

[15] A 27-mW 3.6-Gb/s I/O transceiver [J].

Wong, KLJ ;

Hatamkhani, H ;

Mansuri, M ;

Yang, CKK .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (04) :602-612

[16] A 1.8-v 700-Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration [J].

Yoo, CS ;

Kyung, KH ;

Lim, KN ;

Lee, HC ;

Chai, JW ;

Heo, NW ;

Kim, CH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (06) :941-951

[17] A 10 Gb/s BiCMOS adaptive cable equalizer [J].

Zhang, GYE ;

Green, MM .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (11) :2132-2140

← 1 2 →