Evolvable platform for array processing: A one-chip approach

The crossbreeding between advanced microprocessor design and Field Programmable Gate AI-rays (FPGAs) has produced the Field Programmable Processor Array: code named FPPA. The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a I Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principle, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.