Low-power and high-speed ROM modules for ASIC applications

被引：8

作者：

Chang, CR ^{[1
]}

Wang, JS ^{[1
]}

Yang, CH ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2001年 / 36卷 / 10期

关键词：

high speed; low power; NHS-PDCMOS; pseudo-footless dynamic CMOS logic decoder; ROM; selective precharge;

D O I：

10.1109/4.953480

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe in this paper the design of a set of low-power and high-speed NOR-type ROM modules suitable for embedded applications in ASICs or SOCs. The circuit is derived from the four-phase high-speed precharge-discharge dynamic CMOS logic (NHS-PDCMOS) with the number of operational phases reduced from four to one. This. facilitates the interconnections to other system blocks that are usually designed to be one phase. Experimental results show that for the size of 2K x 8, the proposed high-speed ROM module is about 1.89 times faster, consumes 21% less power, and occupies similar silicon area as compared to a conventional design. Also for the same size, the proposed low-power ROM module is 1.17 times faster, 14% smaller, and consumes 83% less power as compared to the conventional design.

引用

页码：1516 / 1523

页数：8

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