Integrating HW/SW partitioning and architecture exploration for system level design

An efficient system-level design is a crucial step in the Systems-on-Chip paradigm because it is becoming the most important source of desired solutions. In this paper we concentrate on integrating Hardware/Software partitioning and architecture exploration to support an idea called "from concept to implementation" in electronic design industry. This design methodology proposes to generate a SystemC-based executable model of the system to bridge a gap between the algorithm and the architecture activities. The proposed integration framework is addressed by 1) adaptive granularity HW/SW partitioning and 2) tuning-incremental architecture exploration, so that the imposed constraints, like potential for communication topology and interface incompatibility, are considered in these two levels simultaneously. The effectiveness of this approach is illustrated by a JPEG decoder example.