Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor

被引:9
作者
Jeon, Chang-Hoon [1 ]
Park, Jun-Young [1 ]
Seol, Myeong-Lok [1 ]
Moon, Dong-Il [1 ]
Hur, Jae [1 ]
Bae, Hagyoul [1 ]
Jeon, Seung-Bae [1 ]
Choi, Yang-Kyu [1 ]
机构
[1] Korea Adv Inst Sci & Technol, Sch Elect Engn, Daejeon 34141, South Korea
基金
新加坡国家研究基金会;
关键词
Gate-all-around (GAA) transistor; Joule heating; junctionless (JL) MOSFET; local annealing; silicon nanowire (Si-NW);
D O I
10.1109/TED.2016.2551751
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Thermal engineering assisted by electrical annealing was applied to enhance the device performance of a gate-all-around (GAA) silicon nanowire (Si-NW) transistor. The ON-state current is increased by four times. Joule heating was produced in a Si-NW by electrical biasing. The heating was concentrated on both edges of the gate, which served as a heat sink, effectively lowering the parasitic external resistance of the GAA Si-NW transistor. The electrical biasing gives rise to a thermal annealing effect on a selected device and to all devices connected by a common biasing electrode. The evidence reported in our previous work regarding current-induced oxidation by Joule heating in a Si-NW was also observed in the measured transfer characteristics of the GAA Si-NW transistor in this paper.
引用
收藏
页码:2288 / 2292
页数:5
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