Multi-stage Pulse Shrinking Time-to-Digital Converter for time interval measurements

被引：0

作者：

Liu, Yue ^{[1
]}

Vollenbruch, Ulrich ^{[2
]}

Chen, Yangjian ^{[2
]}

Wicpalek, Christian ^{[3
]}

Maurert, Linus ^{[4
]}

Boos, Zdravko ^{[5
]}

Weigel, Robert ^{[6
]}

机构：

[1] Univ Linz, Res Inst Integrated Circuits, Linz, Austria

[2] Linz Ctr Mechatron GmbH, Linz, Austria

[3] Univ Linz, Inst Commun & Informat Engn, Linz, Austria

[4] DICE GmbH & Co KG, Linz, Austria

[5] Infineon Technol AG, Neubiberg, Germany

[6] Univ Erlangen Nurnberg, Inst Elect Engn, Erlangen, Germany

来源：

2007 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, VOLS 1 AND 2 | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new structure of Pulse Shrinking Time-to-Digital Converter (TDC) with 20ps resolution which is implemented in Infineon 0.13 mu m CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as Phase Detector for Phase Locked Loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.

引用

收藏

页码：382 / +

页数：2

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