A Fully Integrated X-Band Phased-Array Transceiver in 0.13-μm CMOS Technology

This paper presents an X-band common-leg phased-array transceiver in 0.13-mu m CMOS technology. The design based on the all-RF architecture contains a 6-bit phase shifter (PS), a 6-bit attenuator, single pole double through switches (SPDT), a low-noise amplifier (LNA), a power amplifier (PA), and several loss compensation amplifiers (LCA). The phased-array transceiver achieves a 31.5 dB gain adjustment range with 0.5 dB step in RX path and 360 degrees phase adjustment range with 5.625 degrees resolution in both RX/TX paths. In the receive mode, the receiver demonstrates a gain of 12 dB, root means square (RMS) phase error less than 43 degrees, and an RMS gain error less than 0.44 dB, from 9 to 10.5 GHz, with 120-mW de power consumption. In the transmit mode, the transmitter achieves a gain of 20 dB, an output P-1dB of 9.7dBm, and an RMS phase error less than 3.8 degrees, from 9 to 10.5 GHz, with 250-mW de power consumption. The whole transceiver occupies a 3.9x4.4 mm(2) chip area, including the testing pads.