A fractional-N PLL frequency synthesizer design

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using 3rd order DS modulator for 915MHz medium speed FSK wireless link. The voltage-controlled oscillator (VCO), pre-scaler of divide-by-8, phase frequency detector (PFD), and charge pump (CP) have been developed with 0.25-mm CMOS process. A 3rd order external loop filter has been optimized to reduce the lock-in time. The fractional-N divider and 3rd order DS modulator have been designed with the VHDL codes, and implemented through the FPGA board of the Xilinx Spartan2E. The VCO has been designed to span from 900MHz to 950MHz band using LC resonator, and a fractional-N divider uses a 36137 modulus and 3rd order DS modulator to reduce the fractional spur. The measured result shows that the RF output power of the frequency synthesizer is -10dBm, the phase noise is -78dBclHz at 100KHz offset frequency, the minimum frequency step is 10kHz, and the maximum lock-in time is around 800ms with 10MHz step change.