Three dimensional CMOS integrated circuits on large grain polysilicon films

被引:29
作者
Chan, VWC [1 ]
Chan, PCH [1 ]
Chan, M [1 ]
机构
[1] Hong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R China
来源
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年
关键词
D O I
10.1109/IEDM.2000.904283
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.
引用
收藏
页码:161 / 164
页数:4
相关论文
共 4 条
  • [1] Abou-Samra SJ, 1998, 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, P54, DOI 10.1109/LPE.1998.708155
  • [2] JAGAR S, 1999, 1999 IEDM, P293
  • [3] High-performance germanium-seeded laterally crystallized TFT's for vertical device integration
    Subramanian, V
    Saraswat, KC
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (09) : 1934 - 1939
  • [4] YAMAZAKI K, 1990, 1990 IEDM, P599