Three dimensional CMOS integrated circuits on large grain polysilicon films
被引:29
作者:
Chan, VWC
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机构:
Hong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R ChinaHong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R China
Chan, VWC
[1
]
Chan, PCH
论文数: 0引用数: 0
h-index: 0
机构:
Hong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R ChinaHong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R China
Chan, PCH
[1
]
Chan, M
论文数: 0引用数: 0
h-index: 0
机构:
Hong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R ChinaHong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R China
Chan, M
[1
]
机构:
[1] Hong Kong Univ Sci & Technol, EEE, Hong Kong, Hong Kong, Peoples R China
来源:
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST
|
2000年
关键词:
D O I:
10.1109/IEDM.2000.904283
中图分类号:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号:
0808 ;
0809 ;
摘要:
In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.
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页码:161 / 164
页数:4
相关论文
共 4 条
[1]
Abou-Samra SJ, 1998, 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, P54, DOI 10.1109/LPE.1998.708155