Vertical nanowire III-V MOSFETs with improved high-frequency gain

被引:13
作者
Kilpi, O. -P. [1 ]
Hellenbrand, M. [1 ]
Svensson, J. [1 ]
Lind, E. [1 ]
Wernersson, L. -E. [1 ]
机构
[1] Lund Univ, Dept Elect & Informat Technol, Box 118, S-22100 Lund, Sweden
基金
欧盟地平线“2020”; 瑞典研究理事会;
关键词
gallium arsenide; III-V semiconductors; indium compounds; nanowires; MOSFET; nanoelectronics; semiconductor heterojunctions; semiconductor quantum wires; vertical nanowire III-V MOSFET; improved high-frequency gain; high-frequency performance; gate-last configuration; device architecture; power gain; asymmetric capacitances; vertical heterostructure nanowire MOSFET; size; 120; 0; nm; frequency; GHz; 130; 20; gain; 14; 4; dB; Si; InAs-InGaAs; TRANSCONDUCTANCE;
D O I
10.1049/el.2020.0266
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High-frequency performance of vertical InAs/InGaAs heterostructure nanowire MOSFETs on Si is demonstrated for the first time for a gate-last configuration. The device architecture allows highly asymmetric capacitances, which increases the power gain. A device withL(g)= 120 nm demonstratesf(T)= 120 GHz,f(max)= 130 GHz and maximum stable gain (MSG) = 14.4 dB at 20 GHz. These metrics demonstrate the state-of-the-art performance of vertical nanowire MOSFETs.
引用
收藏
页码:669 / 671
页数:3
相关论文
共 13 条
  • [1] Topology-Constrained Layered Tracking with Latent Flow
    Chang, Jason
    Fisher, John W., III
    [J]. 2013 IEEE INTERNATIONAL CONFERENCE ON COMPUTER VISION (ICCV), 2013, : 161 - 168
  • [2] Nanometre-scale electronics with III-V compound semiconductors
    del Alamo, Jesus A.
    [J]. NATURE, 2011, 479 (7373) : 317 - 323
  • [3] Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements
    Esfeh, B. Kazemi
    Kilchytska, V.
    Barral, V.
    Planes, N.
    Haond, M.
    Flandre, D.
    Raskin, J. -P.
    [J]. SOLID-STATE ELECTRONICS, 2016, 117 : 130 - 137
  • [4] High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates
    Johansson, Sofia
    Memisevic, Elvedin
    Wernersson, Lars-Erik
    Lind, Erik
    [J]. IEEE ELECTRON DEVICE LETTERS, 2014, 35 (05) : 518 - 520
  • [5] A High-Frequency Transconductance Method for Characterization of High-κ Border Traps in III-V MOSFETs
    Johansson, Sofia
    Berg, Martin
    Persson, Karl-Magnus
    Lind, Erik
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (02) : 776 - 781
  • [6] Kilpi OP, 2017, INT EL DEVICES MEET
  • [7] Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si
    Kilpi, Olli-Pekka
    Svensson, Johannes
    Wu, Jun
    Persson, Axel R.
    Wallenberg, Reine
    Lind, Erik
    Wernersson, Lars-Erik
    [J]. NANO LETTERS, 2017, 17 (10) : 6006 - 6010
  • [8] Record Maximum Transconductance of 3.45 mS/μm for III-V FETs
    Lin, Jianqiang
    Cai, Xiaowei
    Wu, Yufei
    Antoniadis, Dimitri A.
    del Alamo, Jesus A.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2016, 37 (04) : 381 - 384
  • [9] High frequency III-V nanowire MOSFETs
    Lind, Erik
    [J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2016, 31 (09)
  • [10] A Distributed Model for Border Traps in Al2O3 - InGaAs MOS Devices
    Yuan, Yu
    Wang, Lingquan
    Yu, Bo
    Shin, Byungha
    Ahn, Jaesoo
    McIntyre, Paul C.
    Asbeck, Peter M.
    Rodwell, Mark J. W.
    Taur, Yuan
    [J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32 (04) : 485 - 487