FinFET-based SRAM design

被引：95

作者：

Guo, Z ^{[1
]}

Balasubramanian, S ^{[1
]}

Zlatanovici, R ^{[1
]}

King, TJ ^{[1
]}

Nikolic, B ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2005年

关键词：

memory; SRAM; low power; double gate transistors;

D O I：

10.1109/LPE.2005.195476

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Up to 2x improvement in SNM can be achieved in 6-T FinFET-based SRAM cells. A 4-T FinFET-based SRAM cell with built-in feedback can achieve sub-100pA per-cell standby current and offer the similar improvements in SNM as the 6-T cell with feedback, making them attractive for low-power, low-voltage applications.

引用

页码：2 / 7

页数：6

共 20 条

[11]

Nowak EJ, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P411, DOI 10.1109/IEDM.2002.1175866

[12]

PILO H, 2005, SRAM DESIGN NANOSCAL

[13]

QIN H, 2004, ISQED

[14]

SEEVINCK E, 1987, JSSC, P366

[15]

*SYN INC, TAUR V 2003 12

[16]

WUU J, 2005, ISSCC, P488

[17] Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology [J].

Yamaoka, M ;

Osada, K ;

Tsuchiya, R ;

Horiuchi, M ;

Kimura, S ;

Kawahara, T .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :288-291

[18] Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics [J].

Yang, M ;

Gusev, EP ;

Ieong, MK ;

Gluschenkov, O ;

Boyd, DC ;

Chan, KK ;

Kozlowski, PM ;

D'Emic, CP ;

Sicina, RM ;

Jamison, PC ;

Chou, AI .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (05) :339-341

[19] A fully synchronized, pipelined, and re-configurable 50Mb SRAM on 90nm CMOS technology for logic applications [J].

Zhang, K ;

Bhattacharya, U ;

Ma, L ;

Ng, Y ;

Zheng, B ;

Bohr, M ;

Thompson, S .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :253-254

[20]

ZHANG K, 2005, ISSCC FEB, P474

← 1 2 →