FinFET-based SRAM design

被引：95

作者：

Guo, Z ^{[1
]}

Balasubramanian, S ^{[1
]}

Zlatanovici, R ^{[1
]}

King, TJ ^{[1
]}

Nikolic, B ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA

来源：

ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2005年

关键词：

memory; SRAM; low power; double gate transistors;

D O I：

10.1109/LPE.2005.195476

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Up to 2x improvement in SNM can be achieved in 6-T FinFET-based SRAM cells. A 4-T FinFET-based SRAM cell with built-in feedback can achieve sub-100pA per-cell standby current and offer the similar improvements in SNM as the 6-T cell with feedback, making them attractive for low-power, low-voltage applications.

引用

页码：2 / 7

页数：6

共 20 条

[1]

ASENOV A, IEEE TED, V50, P1837

[2] The impact of intrinsic device fluctuations on CMOS SRAM cell stability [J].

Bhavnagarwala, AJ ;

Tang, XH ;

Meindl, JD .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) :658-665

[3]

DEVOIVRE T, 2002, MTDT, P157

[4]

Huang X., 1999, IEDM Tech. Dig, P67, DOI DOI 10.1109/IEDM.1999.823848

[5]

IEONG M, 2001, IEDM

[6] A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 μm generation and desirable for ultra high speed operation [J].

Ishida, M ;

Kawakami, T ;

Tsuji, A ;

Kawamoto, N ;

Motoyoshi, M ;

Ouchi, N .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :201-204

[7]

Joshi RV, 2004, ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, P211

[8] Leakage and process variation effects in current testing on future CMOS circuits [J].

Keshavarzi, A ;

Tschanz, JW ;

Narendra, S ;

De, V ;

Roy, K ;

Hawkins, CF ;

Daasch, WR ;

Sachdev, M .

IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (05) :36-43

[9] CMOS vertical multiple independent Gate Field Effect Transistor (MIGHT) [J].

Mathew, L ;

Du, Y ;

Thean, AVY ;

Sadd, M ;

Vandooren, A ;

Parker, C ;

Stephens, T ;

Mora, R ;

Rai, R ;

Zavala, M ;

Sing, D ;

Kalpat, S ;

Hughes, J ;

Shimer, R ;

Jallepalli, S ;

Workman, G ;

Zhang, W ;

Fossum, JG ;

White, BE ;

Nguyen, BY ;

Mogab, J .

2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, :187-189

[10] Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement [J].

Mukhopadhyay, S ;

Mahmoodi-Meimand, H ;

Roy, K .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :64-67

← 1 2 →