Innovating SOI memory devices based on floating-body effects

被引：27
作者：
Bawedin, M.
CristoloveanU, S.
Flandre, D.
机构：
[1] Catholic Univ Louvain, Microelect Lab, B-1348 Louvain, Belgium
[2] MINATEC, INP Grenoble, IMEP, Grenoble 38016, France
来源：
SOLID-STATE ELECTRONICS | 2007年 / 51卷 / 10期
关键词：
IT-DRAM; capacitor-less; MSD effect; SOI; floating-body; memory;
D O I：
10.1016/j.sse.2007.06.024
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Scaling considerations of conventional DRAMs lead to recent developments of capacitor-less, single-transistor (1T) DRAM based on the floating-body effects in SOI transistors. Several options (Z-RAM and TTRAM) are reviewed and discussed in terms of operation mechanisms, performance and scaling. We also describe a new concept of 1T-DRAM (named MSDRAM) simple to fabricate, program and read. Its basic mechanism is the meta-stable dip (MSD) hysteresis effect which takes advantage of the coupling between front and back interfaces in SOI transistors. Systematic measurements show that MSDRAMs are suitable for low-power applications as they exhibit negligible off-state current, long retention time and scalability. (C) 2007 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1252 / 1262
页数：11
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