60 GHz Low Noise Amplifiers with 1 kV CDM protection in 40 nm LP CMOS

被引：0
|
作者：
Raczkowski, Kuba [1 ,2 ]
Thijs, Steven [1 ]
Tseng, Jen-Chou [3 ]
Chang, Tzu-Heng [3 ]
Song, Ming-Hsiang [3 ]
Linten, Dimitri [1 ]
Nauwelaers, Bart [2 ]
Wambacq, Piet [1 ]
机构：
[1] Imec, Heverlee, Belgium
[2] Katholieke Univ Leuven, Leuven, Belgium
[3] TSMC, Hsinchu, Taiwan
来源：
2012 IEEE 12TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF) | 2012年
关键词：
ALGORITHMIC DESIGN; ESD PROTECTION;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a set of miniature, three-stage 60 GHz LNAs designed in 40 nm LP CMOS. The designs prove effectiveness and ease of use of inductor-based ESD protection schemes applied to mm-wave circuits. The measured ESD protection levels reach 4.5 kV HBM, up to 7.6 A for VFTLP tests and a record of 1 kV CDM. At the same time, the NF of the LNAs is below 8 dB and the gain above 15 dB at 60 GHz, all at 1.1 V supply. These circuits can effectively be used as input stages of a phased array receiver.
引用
收藏
页码：9 / 12
页数：4
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